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1/37 october 2004 m95040 m95020, m95010 4kbit, 2kbit and 1kbit serial spi bus eeprom with high speed clock features summary compatible with spi bus serial interface (positive clock spi modes) single supply voltage: ? 4.5 to 5.5v for m950x0 ? 2.5 to 5.5v for m950x0-w ? 1.8 to 5.5v for m950x0-r high speed ? 10mhz clock rate, 5ms write time status register byte and page write (up to 16 bytes) self-timed programming cycle adjustable size read-only eeprom area enhanced esd protection more than 1 million erase/write cycles more than 40-year data retention table 1. product list figure 1. packages reference part number m95040 m95040 m95040-w m95040-r m95020 m95020 m95020-w m95020-r m95010 m95010 m95010-w m95010-r so8 (mn) 150 mil width pdip8 (bn) 8 1 tssop8 (dw) 169 mil width 8 1
m95040, m95020, m95010 2/37 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. dip, so and tssop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data output (q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chip select (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 hold (hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write protect (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. bus master and memory devices on the spi bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. write enable (wren) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3/37 m95040, m95020, m95010 write disable (wrdi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 read status register (rdsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10.read status register (rdsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11.write status register (wrsr) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12.read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 13.byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14.page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power-up and delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. operating conditions (m950x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. operating conditions (m950x0-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. operating conditions (m950x0-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. dc characteristics (m950x0, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. dc characteristics (m950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. dc characteristics (m950x0-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. dc characteristics (m950x0-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17. dc characteristics (m950x0-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18. ac characteristics (m950x0, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19. ac characteristics (m950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 20. ac characteristics (m950x0-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21. ac characteristics (m950x0-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 22. ac characteristics (m950x0-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16.serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17.hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18.output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19.pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline . . . . . . . . . . . . . . . . . 32
m95040, m95020, m95010 4/37 table 23. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data . . . . . . . . . . 32 figure 20.so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . 33 table 24. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data 33 figure 21.tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . 34 table 25. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . 34 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 26. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 table 27. how to identify present and previous products by the process identification letter . . . 35 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 28. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5/37 m95040, m95020, m95010 summary description the m95040 is a 4 kbit (512 x 8) electrically eras- able programmable memory (eeprom), access- ed by a high speed spi-compatible bus. the other members of the family (m95020 and m95010) are identical, though proportionally smaller (2 and 1 kbit, respectively). each device is accessed by a simple serial inter- face that is spi-compatible. the bus signals are c, d and q, as shown in table 2. and figure 2. . the device is selected when chip select (s ) is tak- en low. communications with the device can be interrupted using hold (hold ). write instruc- tions are disabled by write protect (w ). figure 2. logic diagram figure 3. dip, so and tssop connections note: see package mechanical section for package dimen- sions, and how to identify pin-1. table 2. signal names ai01789c s v cc m95xxx hold v ss w q c d c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground d v ss c hold q sv cc w ai01790d m95xxx 1 2 3 4 8 7 6 5
m95040, m95020, m95010 6/37 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals can be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in table 13. to table 17. ). these signals are described next. serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling e dge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives in- structions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, address- es, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select (s ). when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the stand- by power mode. driving chip select (s ) low se- lects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. hold (hold ). the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be se- lected, with chip select (s ) driven low. write protect (w ). this input signal is used to control whether the memory is write protected. when write protect (w ) is held low, writes to the memory are disabled, but other operations remain enabled. write protect (w ) must either be driven high or low, but must not be left floating.
7/37 m95040, m95020, m95010 connecting to the spi bus these devices are fully compatible with the spi protocol. all instructions, addresses and input data bytes are shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select (s ) goes low. all output data bytes are shifted out of the device, most significant bit first. the serial data output (q) is latched on the firs t falling edge of the serial clock (c) after the instruction (such as the read from memory array and read status register in- structions) have been clocked into the device. figure 4. shows three devices, connected to an mcu, on a spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, all the others being high impedance. figure 4. bus master and memory devices on the spi bus note: the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. ai03746d bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold
m95040, m95020, m95010 8/37 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 5. , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 5. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
9/37 m95040, m95020, m95010 operating features power-up when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s ) must be al- lowed to follow the v cc voltage. it must not be al- lowed to float, but should be connected to v cc via a suitable pull-up resistor. as a built in safety feature, chip select (s ) is edge sensitive as well as level sensitive. after power- up, the device does not become selected until a falling edge has first been detected on chip select (s ). this ensures that chip select (s ) must have been high, prior to going low to start the first op- eration. power-down at power-down, the device must be deselected. chip select (s ) should be allowed to follow the voltage applied on v cc . active power and standby power modes when chip select (s ) is low, the device is select- ed, and in the active power mode. the device consumes i cc , as specified in table 13. to table 17. . when chip select (s ) is high, the device is dese- lected. if an erase/write cycle is not currently in progress, the device then goes in to the standby power mode, and the device consumption drops to i cc1 . hold condition the hold (hold ) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device must be selected, with chip select (s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the de- vice while it is in the hold condition, has the effect of resetting the state of the device, and this mech- anism can be used if it is required to reset any pro- cesses that had been in progress. the hold condition starts when the hold (hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in figure 6. ). the hold condition ends when the hold (hold ) signal is driven high at the same time as serial clock (c) already being low. figure 6. also shows what happens if the rising and falling e dges are not timed to coincide with serial clock (c) being low. figure 6. hold condition activation ai02029d hold c hold condition hold condition
m95040, m95020, m95010 10/37 status register figure 7. shows the position of the status register in the control logic of the device. this register con- tains a number of control bits and status bits, as shown in table 3. . bits b7, b6, b5 and b4 are always read as 1. wip bit. the write in progress bit is a volatile read-only bit that is automatically set and reset by the internal logic of the device. when set to a 1, it indicates that the memory is busy with a write cy- cle. wel bit. the write enable latch bit is a volatile read-only bit that is set and reset by specific in- structions. when reset to 0, no write or wrsr instructions are accepted by the device. bp1, bp0 bits. the block protect bits are non- volatile read-write bits. these bits define the area of memory that is protected against the execution of write cycles, as summarized in table 4. . table 3. status register format data protection and protocol control to help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. the main security measures can be summarized as follows: ? the wel bit is reset at power-up. ? chip select (s ) must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the memory array or in the status register). ? accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. ? invalid chip select (s ) and hold (hold ) transitions are ignored. for any instruction to be accepted and executed, chip select (s ) must be driven high after the rising edge of serial clock (c) that latches the last bit of the instruction, and before the next rising edge of serial clock (c). for this, ?the last bit of the instruction? can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (ex- cept in the case of rdsr and read instructions). moreover, the "next rising edge of clock" might (or might not) be the next bus transaction for some other device on the bus. when a write cycle is in progress, the device pro- tects it against external interruption by ignoring any subsequent read, write or wrsr instruc- tion until the present cycle is complete. table 4. write-protected block size b7 b0 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bit write in progress bit status register bits protected block array addresses protected bp1 bp0 m95040 m95020 m95010 0 0 none none none none 0 1 upper quarter 180h - 1ffh c0h - ffh 60h - 7fh 1 0 upper half 100h - 1ffh 80h - ffh 40h - 7fh 1 1 whole memory 000h - 1ffh 00h - ffh 00h - 7fh
11/37 m95040, m95020, m95010 memory organization the memory is organized as shown in figure 7. . figure 7. block diagram ai01272c hold s w control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder c d q size of the read only eeprom area status register
m95040, m95020, m95010 12/37 instructions each instruction starts with a single-byte code, as summarized in table 5. . if an invalid instruction is sent (one not contained in table 5. ), the device automatically deselects it- self. table 5. instruction set note: 1. a8 = 1 for the upper half of the memory array of the m95040, and 0 for the lower half, and is don?t care for other devices. 2. x = don?t care. instruc tion description instruction format wren write enable 0000 x110 wrdi write disable 0000 x100 rdsr read status register 0000 x101 wrsr write status register 0000 x001 read read from memory array 0000 a 8 011 write write to memory array 0000 a 8 010
13/37 m95040, m95020, m95010 write enable (wren) the write enable latch (wel) bit must be set pri- or to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 8. , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) being driven high. figure 8. write enable (wren) sequence write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 9. , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) be- ing driven high. the write enable latch (wel) bit, in fact, be- comes reset by any of the following events: ?power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion ? write protect (w ) line being held low. figure 9. write disable (wrdi) sequence c d ai01441d s q 2 1 34567 high impedance 0 instruction c d ai03790d s q 2 1 34567 high impedance 0 instruction
m95040, m95020, m95010 14/37 read status register (rdsr) one of the major uses of this instruction is to allow the mcu to poll the state of the write in progress (wip) bit. this is needed because the device will not accept further write or wrsr instructions when the previous write cycle is not yet finished. as shown in figure 10. , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte are then shifted in, on serial data input (d). the current state of the bits in the status register is shifted out, on serial data out (q). the read cycle is terminated by driving chip select (s ) high. the status register may be read at any time, even during a write cycle (whether it be to the memory area or to the status register). all bits of the sta- tus register remain valid, and can be read using the rdsr instruction. however, during the current write cycle, the values of the non-volatile bits (bp0, bp1) become frozen at a constant value. the updated value of these bits becomes avail- able when a new rdsr instruction is executed, af- ter completion of the write cycle. on the other hand, the two read-only bits (write enable latch (wel), write in progress (wip)) are dynamically updated during the on-going write cycle. the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write or write status register in- struction is accepted. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written with the write status regis- ter (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the rele- vant memory area (as defined in table 4. ) be- comes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protect- ed mode has not been set. figure 10. read status register (rdsr) sequence c d s 2 1 3456789101112131415 instruction 0 ai01444d q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
15/37 m95040, m95020, m95010 write status register (wrsr) this instruction has no effect on bits b7, b6, b5, b4, b1 and b0 of the status register. as shown in figure 11. , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and data byte are then shifted in on serial data input (d). the instruction is terminated by driving chip se- lect (s ) high. chip select (s ) must be driven high after the rising edge of serial clock (c) that latch- es the eighth bit of the data byte, and before the the next rising edge of serial clock (c). if this con- dition is not met, the write status register (wrsr) instruction is not executed. the self- timed write cycle starts, and continues for a peri- od t w (as specified in table 18. to table 22. ), at the end of which the write in progress (wip) bit is reset to 0. the instruction is not accepted, and is not execut- ed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the device has not been deselected, by chip select (s ) being driven high, after the eighth bit, b0, of the data byte has been latched in ? if write protect (w ) is low. figure 11. write status register (wrsr) sequence c d ai01445b s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m95040, m95020, m95010 16/37 read from memory array (read) as shown in figure 12. , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and address byte are then shifted in, on serial data input (d). for the m95040, the most significant address bit, a8, is in- corporated as bit b3 of the instruction byte, as shown in table 5. . the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s ) continues to be driven low, an internal bit-pointer is automatically incremented at each clock cycle, and t he corresponding data bit is shifted out. when the highest address is reached, the address counter rolls over to ze ro, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruc- tion. the read cycle is terminated by driving chip se- lect (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not execut- ed, if a write cycle is currently in progress. table 6. address range bits figure 12. read from memory array (read) sequence note: depending on the memory size, as shown in table 6. , the most significant address bits are don?t care. device m95040 m95020 m95010 address bits a8-a0 a7-a0 a6-a0 c d ai01440e s q a7 2 1 345678910111213141516171819 a6 a5 a4 a3 a2 a1 a0 a8 20 21 22 76543 2 0 1 high impedance data out instruction byte address 0
17/37 m95040, m95020, m95010 write to memory array (write) as shown in figure 13. , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip se- lect (s ) high after the rising edge of serial clock (c) that latches the last data bit, and before the next rising edge of serial clock (c) occurs any- where on the bus. in the case of figure 13. , this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in table 18. to table 22. ), at the end of which the write in progress (wip) bit is reset to 0. if, though, chip select (s ) continues to be driven low, as shown in figure 14. , the next byte of input data is shifted in. in this way, all the bytes from the given address to the end of the same page can be programmed in a single instruction. if chip select (s ) still continues to be driven low, the next byte of input data is shifted in, and is used to overwrite the byte at the start of the current page. the instruction is not accepted, and is not execut- ed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the device has not been deselected, by chip select (s ) being driven high, at a byte boundary (after the rising edge of serial clock (c) that latches the last data bit, and before the next rising edge of serial clock (c) occurs anywhere on the bus) ? if write protect (w ) is low or if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. figure 13. byte write (write) sequence note: depending on the memory size, as shown in table 6. , the most significant address bits are don?t care. ai01442d c d s q a7 2 1 345678910111213141516171819 a6 a5 a4 a3 a2 a1 a0 a8 20 21 22 23 high impedance instruction byte address 0 765432 0 1 data byte
m95040, m95020, m95010 18/37 figure 14. page write (write) sequence note: depending on the memory size, as shown in table 6. , the most significant address bits are don?t care. c d s 2 1 345678910111213141516171819 20 21 22 23 instruction byte address 0 data byte 1 c d ai01443d s 26 25 27 28 29 30 31 8+8n 24 data byte 16 9+8n 10+8n 11+8n 12+8n 13+8n 14+8n 15+8n 136 137 138 139 140 141 142 143 data byte n 76 3210 54 data byte 2 7 a7 a6 a5 a4 a3 a2 a1 a0 a8 765432 0 1 7 6543210765432 0 1
19/37 m95040, m95020, m95010 power-up and delivery state power-up state after power-up, the device is in the following state: ? low power standby power mode ? deselected (after power-up, a falling edge is required on chip select (s ) before any instructions can be started). ? not in the hold condition ? the write enable latch (wel) is reset to 0 ? write in progress (wip) is reset to 0 the bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). initial delivery state the device is delivered with the memory array set at all 1s (ffh). the block protect (bp1 and bp0) bits are initialized to 0.
m95040, m95020, m95010 20/37 maximum rating stressing the device outside the ratings listed in table 7. may cause permanent damage to the de- vice. these are stress ratings only, and operation of the device at these, or any other conditions out- side those indicated in the operating sections of this specification, is not implied. exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 7. absolute maximum ratings note: 1. compliant with jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 2. aec-q100-002 (compliant with jedec std jesd22-a114a, c1=100pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering 1 see note 1 c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) 2 ?4000 4000 v
21/37 m95040, m95020, m95010 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 8. operating conditions (m950x0) table 9. operating conditions (m950x0-w) table 10. operating conditions (m950x0-r) table 11. ac measurement conditions note: output hi-z is defined as the point where data out is no longer driven. figure 15. ac measurement i/o waveform symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
m95040, m95020, m95010 22/37 table 12. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 5mhz. table 13. dc characteristics (m950x0, device grade 6) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. 2. previous product: identified by process identification letter k. 3. present product: identified by process identification letter w or g. symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (d) v in = 0v 8 pf input capacitance (other pins) v in = 0v 6 pf symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c=0.1v cc /0.9v cc at 5mhz, v cc = 5 v, q = open, previous product 2 5ma c = 0.1v cc /0.9v cc at 10mhz, v cc = 5 v, q = open, present product 3 5ma i cc1 supply current (standby power mode) s = v cc , v cc = 5 v, v in = v ss or v cc , previous product 2 10 a s = v cc , v cc = 5 v, v in = v ss or v cc , present product 3 2a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol 1 output low voltage i ol = 2 ma, v cc = 5 v 0.4 v v oh 1 output high voltage i oh = ?2 ma, v cc = 5v 0.8v cc v
23/37 m95040, m95020, m95010 table 14. dc characteristics (m950x0, device grade 3) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. 2. previous product: identified by process identification letter k. 3. present product: identified by process identification letter w or g. table 15. dc characteristics (m950x0-w, device grade 6) note: 1. previous product: identified by process identification letter k. 2. present product: identified by process identification letter w or g. symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 2 mhz, v cc = 5 v, q = open, previous product 2 5ma c = 0.1v cc /0.9v cc at 5 mhz, v cc = 5 v, q = open, present product 3 3ma i cc1 supply current (standby power mode) s = v cc , v cc = 5 v, v in = v ss or v cc , previous product 2 10 a s = v cc , v cc = 5 v, v in = v ss or v cc , present product 3 5a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol 1 output low voltage i ol = 2 ma, v cc = 5 v 0.4 v v oh 1 output high voltage i oh = ?2 ma, v cc = 5v 0.8v cc v symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 2 mhz, v cc = 2.5 v, q = open, previous product 1 2ma c = 0.1v cc /0.9v cc at 5 mhz, v cc = 2.5 v, q = open, present product 2 2ma i cc1 supply current (standby power mode) s = v cc , v cc = 2.5 v, v in = v ss or v cc , previous product 1 2a s = v cc , v cc = 2.5 v v in = v ss or v cc , present product 2 1a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v 0.4 v v oh output high voltage i oh = ?0.4 ma, v cc = 2.5 v 0.8 v cc v
m95040, m95020, m95010 24/37 table 16. dc characteristics (m950x0-w, device grade 3) note: 1. previous product: identified by process identification letter k. 2. present product: identified by process identification letter w or g. table 17. dc characteristics (m950x0-r) note: 1. preliminary data: product under development. please contact your nearest st sales office for information. symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 2 mhz, v cc = 2.5 v, q = open, previous product 1 2ma c = 0.1v cc /0.9v cc at 5 mhz, v cc = 2.5 v, q = open, present product 2 2ma i cc1 supply current (standby power mode) s = v cc , v cc = 2.5 v, v in = v ss or v cc 2a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v 0.4 v v oh output high voltage i oh = ?0.4 ma, v cc = 2.5 v 0.8 v cc v symbol parameter test condition min. 1 max. 1 unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c=0.1v cc /0.9. v cc at 1 mhz, v cc = 1.8 v, q = open 1ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc , v cc = 1.8 v 0.5 a v il input low voltage ?0.45 0.25 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8 v 0.8 v cc v
25/37 m95040, m95020, m95010 table 18. ac characteristics (m950x0, device grade 6) note: 1. t ch + t cl must never be less than the shortest possible clock period, 1 / f c (max) 2. value guaranteed by characterization, not 100% tested in production. 3. previous product: identified by process identification letter k. 4. present product: identified by process identification letter w or g. test conditions specified in table 11. and table 8. symbol alt. parameter min. 3 max. 3 min. 4 max. 4 unit f c f sck clock frequency d.c. 5 d.c. 10 mhz t slch t css1 s active setup time 90 15 ns t shch t css2 s not active setup time 90 15 ns t shsl t cs s deselect time 100 40 ns t chsh t csh s active hold time 90 25 ns t chsl s not active hold time 90 15 ns t ch 1 t clh clock high time 90 40 ns t cl 1 t cll clock low time 90 40 ns t clch 2 t rc clock rise time 1 1 s t chcl 2 t fc clock fall time 1 1 s t dvch t dsu data in setup time 20 15 ns t chdx t dh data in hold time 30 15 ns t hhch clock low hold time after hold not active 70 15 ns t hlch clock low hold time after hold active 40 20 ns t chhl clock high set-up time before hold active t ch 30 ns t chhh clock high set-up time before hold not active t ch 30 ns t shqz 2 t dis output disable time 100 25 ns t clqv t v clock low to output valid 60 35 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 50 20 ns t qhql 2 t fo output fall time 50 20 ns t hhqv t lz hold high to output valid 50 25 ns t hlqz 2 t hz hold low to output high-z 100 35 ns t w t wc write time 10 5 ms
m95040, m95020, m95010 26/37 table 19. ac characteristics (m950x0, device grade 3) note: 1. t ch + t cl must never be less than the shortest possible clock period, 1 / f c (max) 2. value guaranteed by characterization, not 100% tested in production. 3. previous product: identified by process identification letter k. 4. present product: identified by process identification letter w or g. test conditions specified in table 11. and table 8. symbol alt. parameter min. 3 max. 3 min. 4 max. 4 unit f c f sck clock frequency d.c. 2 d.c. 5 mhz t slch t css1 s active setup time 200 90 ns t shch t css2 s not active setup time 200 90 ns t shsl t cs s deselect time 200 100 ns t chsh t csh s active hold time 200 90 ns t chsl s not active hold time 200 90 ns t ch 1 t clh clock high time 200 90 ns t cl 1 t cll clock low time 200 90 ns t clch 2 t rc clock rise time 1 1 s t chcl 2 t fc clock fall time 1 1 s t dvch t dsu data in setup time 40 20 ns t chdx t dh data in hold time 50 30 ns t hhch clock low hold time after hold not active 140 70 ns t hlch clock low hold time after hold active 90 40 ns t chhl clock high set-up time before hold active t ch 60 ns t chhh clock high set-up time before hold not active t ch 60 ns t shqz 2 t dis output disable time 250 100 ns t clqv t v clock low to output valid 150 60 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 100 50 ns t qhql 2 t fo output fall time 100 50 ns t hhqv t lz hold high to output valid 100 50 ns t hlqz 2 t hz hold low to output high-z 250 100 ns t w t wc write time 10 5 ms
27/37 m95040, m95020, m95010 table 20. ac characteristics (m950x0-w, device grade 6) note: 1. t ch + t cl must never be less than the shortest possible clock period, 1 / f c (max) 2. value guaranteed by characterization, not 100% tested in production. 3. previous product: identified by process identification letter k. 4. present product: identified by process identification letter w or g. test conditions specified in table 11. and table 9. symbol alt. parameter min. 3 max. 3 min. 4 max. 4 unit f c f sck clock frequency d.c. 2 d.c. 5 mhz t slch t css1 s active setup time 200 90 ns t shch t css2 s not active setup time 200 90 ns t shsl t cs s deselect time 200 100 ns t chsh t csh s active hold time 200 90 ns t chsl s not active hold time 200 90 ns t ch 1 t clh clock high time 200 90 ns t cl 1 t cll clock low time 200 90 ns t clch 2 t rc clock rise time 1 1 s t chcl 2 t fc clock fall time 1 1 s t dvch t dsu data in setup time 40 20 ns t chdx t dh data in hold time 50 30 ns t hhch clock low hold time after hold not active 140 70 ns t hlch clock low hold time after hold active 90 40 ns t chhl clock high set-up time before hold active t ch 60 ns t chhh clock high set-up time before hold not active t ch 60 ns t shqz 2 t dis output disable time 250 100 ns t clqv t v clock low to output valid 150 60 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 100 50 ns t qhql 2 t fo output fall time 100 50 ns t hhqv t lz hold high to output valid 100 50 ns t hlqz 2 t hz hold low to output high-z 250 100 ns t w t wc write time 10 5 ms
m95040, m95020, m95010 28/37 table 21. ac characteristics (m950x0-w, device grade 3) note: 1. t ch + t cl must never be less than the shortest possible clock period, 1 / f c (max) 2. value guaranteed by characterization, not 100% tested in production. 3. previous product: identified by process identification letter k. 4. present product: identified by process identification letter w or g. test conditions specified in table 11. and table 9. symbol alt. parameter min. 3 max. 3 min. 4 max. 4 unit f c f sck clock frequency d.c. 2 d.c. 5 mhz t slch t css1 s active setup time 200 90 ns t shch t css2 s not active setup time 200 90 ns t shsl t cs s deselect time 200 100 ns t chsh t csh s active hold time 200 90 ns t chsl s not active hold time 200 90 ns t ch 1 t clh clock high time 200 90 ns t cl 1 t cll clock low time 200 90 ns t clch 2 t rc clock rise time 1 1 s t chcl 2 t fc clock fall time 1 1 s t dvch t dsu data in setup time 40 20 ns t chdx t dh data in hold time 50 30 ns t hhch clock low hold time after hold not active 140 70 ns t hlch clock low hold time after hold active 90 40 ns t chhl clock high set-up time before hold active t ch 60 ns t chhh clock high set-up time before hold not active t ch 60 ns t shqz 2 t dis output disable time 250 100 ns t clqv t v clock low to output valid 150 60 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 100 50 ns t qhql 2 t fo output fall time 100 50 ns t hhqv t lz hold high to output valid 100 50 ns t hlqz 2 t hz hold low to output high-z 250 100 ns t w t wc write time 10 5 ms
29/37 m95040, m95020, m95010 table 22. ac characteristics (m950x0-r) note: 1. t ch + t cl must never be less than the shortest possible clock period, 1 / f c (max) 2. value guaranteed by characterization, not 100% tested in production. 3. preliminary data: product under development. please contact your nearest st sales office for information. test conditions specified in table 11. and table 10. symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 2 mhz t slch t css1 s active setup time 200 ns t shch t css2 s not active setup time 200 ns t shsl t cs s deselect time 200 ns t chsh t csh s active hold time 200 ns t chsl s not active hold time 200 ns t ch 1 t clh clock high time 200 ns t cl 1 t cll clock low time 200 ns t clch 2 t rc clock rise time 1 s t chcl 2 t fc clock fall time 1 s t dvch t dsu data in setup time 40 ns t chdx t dh data in hold time 50 ns t hhch clock low hold time after hold not active 140 ns t hlch clock low hold time after hold active 90 ns t chhl clock high set-up time before hold active 120 ns t chhh clock high set-up time before hold not active 120 ns t shqz 2 t dis output disable time 250 ns t clqv t v clock low to output valid 180 ns t clqx t ho output hold time 0 ns t qlqh 2 t ro output rise time 100 ns t qhql 2 t fo output fall time 100 ns t hhqv t lz hold high to output valid 100 ns t hlqz 2 t hz hold low to output high-z 250 ns t w t wc write time 10 ms
m95040, m95020, m95010 30/37 figure 16. serial input timing figure 17. hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai02032b s d hold tchhl thlch thhch tchhh thhqv thlqz
31/37 m95040, m95020, m95010 figure 18. output timing c q ai01449d s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
m95040, m95020, m95010 32/37 package mechanical figure 19. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline note: drawing is not to scale. table 23. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e2.54??0.100?? ea 7.62 ? ? 0.300 ? ? eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
33/37 m95040, m95020, m95010 figure 20. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. table 24. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e1.27??0.050?? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 so-a e n cp b e a d c l a1 1 h h x 45?
m95040, m95020, m95010 34/37 figure 21. tssop8 ? 8 lead thin shrink small outline, package outline note: drawing is not to scale. table 25. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
35/37 m95040, m95020, m95010 part numbering table 26. ordering information scheme note: 1. st strongly recommends the use of the automotive grade devices for use in an automotive environment. the high reliabilit y cer- tified flow (hrcf) is described in the quality note qnee9801. please ask your nearest st sales office for a copy. 2. used only for device grade 3 for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. table 27. how to identify present and previous products by the process identification letter example: m95040 ? w mn 6 t p /w device type m95 = spi serial access eeprom device function 040 = 4 kbit (512 x 8) 020 = 2 kbit (256 x 8) 010 = 1 kbit (128 x 8) operating voltage blank = v cc = 4.5 to 5.5v w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v package bn = pdip8 mn = so8 (150 mil width) dw = tssop8 (169 mil width) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 = device tested with high reliability certified flow 1 . automotive temperature range (?40 to 125 c) option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p = lead-free and rohs compliant g = lead-free, rohs compliant, sb 2 o 3 -free and tbba-free process 2 blank = f6sp20% /w = f6sp36% markings on present products 1 markings on previous products 1 95040w6 ayww w (or ayww g ) 95040w6 ayw w k
m95040, m95020, m95010 36/37 revision history table 28. document revision history date version description of revision 10-may-2000 2.2 s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the byte write operation 16-mar-2001 2.3 human body model meets jedec std (table 2). minor adjustments to figs 7,9,10,11 & tab 9. wording changes, according to the standard glossary illustrations and package mechanical data updated 19-jul-2001 2.4 temperature range ?3? added to the -w supply voltage range in dc and ac characteristics 11-oct-2001 3.0 document reformatted using the new template 26-feb-2002 3.1 description of chip deselect after 8th clock pulse made more explicit 27-sep-2002 3.2 position of a8 in read instruction sequence figure corrected. load capacitance c l changed 24-oct-2002 3.3 minimum values for tchhl and tchhh changed. 24-feb-2003 3.4 description of read from memory array (read) instruction corrected, and clarified 28-may-2003 3.5 new products, identified by the process letter w, added 25-jun-2003 3.6 correction to current products, identified by the process letter k not l. i cc changed in dc characteristics, and t chhl , t chhh substituted in ac characteristics voltage range -s upgraded by removing it, and adding the -r voltage range in its place temperature range 5 removed. 21-nov-2003 4.0 table of contents, and pb-free options added. v il (min) improved to -0.45v 02-feb-2004 4.1 v il (max) and t clqv (max) changed 01-mar-2004 5.0 absolute maximum ratings for v io (min) and v cc (min) improved. soldering temperature information clarified for rohs compliant devices. new 5v and 2.5v devices, with process letter w, promoted from preliminary data to full data. device grade 3 clarified, with reference to hrcf and automotive environments 05-oct-2004 6.0 product list summary table added. process identification letter ?g? information added. order information for tape and reel changed to t. aec-q100-002 compliance. device grade informaton clarified. thhqx corrected to thhqv. signal description updated. 10mhz, 5ms write is now the present product. tch+tcl<1/fc constraint clarified
37/37 m95040, m95020, m95010 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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